The present invention relates generally to low power, relatively high speed (e.g., with sample rates of roughly 100 kilosamples per second (KSPS)) data acquisition circuitry, especially to multi-channel data acquisition circuitry that includes SAR (successive approximation register) ADCs (analog to digital converters).
FIG. 1 shows a SAR ADC conversion circuit 1 which is included in the assignee's commercially available ADS 7866 data acquisition product. SAR ADC conversion circuit 1 receives the amplified output voltage produced by an input amplifier 17. The output of input amplifier 17 can be filtered by an external RC filter 29. Input amplifier 17 receives and amplifies the filtered analog input signal VIN that ultimately is to be digitized. SAR ADC conversion circuit 1 includes a low-power SAR ADC 2 and a conversion and control logic circuit 10.
SAR ADC 2 includes a sample/hold circuit 3 having a (+) input connected to receive the filtered signal VINF produced by filter 29. The (−) input of sample/hold circuit 3 is connected to ground or other suitable reference voltage. The differential output of sample/hold circuit 3 is connected to the inputs of a CDAC (capacitor digital to analog converter) circuit 4 which is controlled via a digital bus 8 by means of a SAR (successive approximation register) 7. The output of CDAC 4, which can include a main CDAC and a dummy CDAC, is coupled to the input of a SAR comparator 5, the output of which is connected by conductor 6 to SAR 7. The resulting digital output DATA of SAR 7 is coupled by a digital bus 9 to conversion and control logic circuit 10.
Conversion and control logic circuit 10 operates in accordance with a serial clock signal SCLK, a power up/down signal CS, a serial data input signal SDI, and a serial data output signal SDO. Bus 25 couples various control signals to SAR 7. A mid-range reference voltage Vmid for SAR comparator 5 is produced by a resistive voltage divider (not shown, but similar to R1, R2 in FIG. 4) which dissipates a substantial amount of power.
Low power SAR ADC 2 in FIG. 1 is switched to a “powered down” state when it is not in the process of digitizing an analog input signal, and is switched to a powered up state only when SAR ADC 2 is required to digitize an analog input signal. The above mentioned resistive voltage divider which supplies a reference voltage Vmid to the input of sample/hold circuit 3 is also powered down and up at the same times as SAR ADC 2. When SAR ADC 2 is switched to its powered up state, it then samples the input analog signal VINF received from input amplifier 17 and filter 29, and then performs an analog to digital conversion of the sampled VINF signal.
Unfortunately, as SAR ADC 2 is being powered up it causes a substantial amount of charge to flow from its input back to the output of input amplifier 17, as does charge left on the capacitors of CDAC 4 from the previous conversion. This causes a power-up “glitch” on the outputs of input amplifier 17 and filter 29, and this power-up glitch must be allowed to settle before accurate sampling of VINF can be accomplished by sample/hold circuit 3 so that accurate digitizing of VINF can be accomplished. The power-up current flow from the ADC input can be thought of as a current transient to filter 29 and amplifier 17 that causes the power-up glitch to be generated. Unfortunately, input amplifier 17 must be a high-bandwidth amplifier, and therefore also must be a high power amplifier, in order to achieve the fast settling of the power-up glitch required for a high data throughput rate before starting the analog to digital conversion of VINF.
FIG. 2 shows a timing diagram of the power up/down signal CS and an internal ADC clock signal ADC CLK which both control the operation of SAR ADC conversion circuit 1 of FIG. 1. SAR ADC 2 is powered up as soon as the falling edge of power up/down signal CS occurs. The analog to digital conversion process by SAR ADC 2 begins at the falling edge of pulse #2 of ADC CLK. Sampling and settling of VINF by sample/hold circuit 3 begins immediately in response to the falling edge of CS and continues during the first two cycles of ADC CLK. Analog to digital conversion begins immediately after the falling edge of pulse #2 of ADC CLK and continues until the falling edge of pulse #15 of ADC CLK. SAR ADC 2 then is powered down immediately after the digital to analog conversion of the sample of VINF is complete, at essentially the same time that the rising edge of CS occurs.
In some prior multi-channel data acquisition systems (not shown), a multiplexer is used to successively route multiple analog input signals to the input of an input amplifier such as amplifier 17, which amplifies the analog input signals and presents an amplified signal to the input of the SAR ADC of the multi-channel data acquisition system. In such multi-channel data acquisition systems it has been necessary to wait until the previous ADC conversion has occurred before switching the multiplexer to the next channel to be sampled.
In such prior multi-channel data acquisition systems, a first analog to digital conversion is completed for the first channel, and only after the conversion of a first analog input signal is complete is the multiplexer switched to a second channel to begin analog to digital conversion of a second analog input signal. A problem with such prior multi-channel data acquisition systems is that to achieve high data throughput rates, it is not only necessary to allow only a very small amount of time for the input amplifier 17 to recover from the above mentioned power-up glitch, but it is also necessary to allow the outputs of the input amplifier 17 and filter 29 to settle to a new voltage level that is proportional to the magnitude of the analog input signal on the second channel to which the multiplexer is to be switched.
Since the only way to achieve the desired small recovery times needed to achieve high data throughput rates for the above described multi-channel data acquisition systems has been to use a high bandwidth (and hence high power) input amplifier, the design of high-speed, low power, multiple-channel data acquisition systems has been very challenging.
Thus, there is an unmet need for a way to reduce the amount of bandwidth and power consumption of an input amplifier which supplies an analog input signal to be sampled for analog to digital conversion by means of a sample-and-hold circuit and an ADC in a data acquisition system.
There also is an unmet need for a way to reduce the amount of bandwidth and power consumption of an input amplifier which supplies an analog input signal to be sampled for analog to digital conversion in a data acquisition system which multiplexes multiple analog input signals into the input amplifier and successively digitizes the analog input signals by means of an ADC, for example a SAR ADC.